Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
نویسندگان
چکیده
Abstract We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in WSe 2 /SnSe Tunnel FETs (TFETs). The energy behavior during charging discharging, together with loss switching cycle efficiency factor are experimentally extracted over broad range temperatures, from cryogenic temperature (77 K) up to 100 °C. obtained results confirm that linear polarizability is maintained all investigated temperature, being inversely proportional T stack. show lower-hysteresis sine-qua-non condition for an improved efficiency, suggesting high interest true NC operation regime. A pulsed measurement technique shows possibility achieve hysteresis-free negative capacitance (NC) effect on 2D/2D TFETs. This enables sub-15 mV dec −1 point subthreshold slope, 20 average swing two decades current, I ON order nA µm −2 / OFF > 10 4 at V d = 1 V. Moreover, smaller than 1.5 current also TFET hysteresis An analog factor, 50 , achieved NC-TFETs. reported highlight operating steep slope switch may allow combined low loss,
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ژورنال
عنوان ژورنال: npj 2D materials and applications
سال: 2021
ISSN: ['2397-7132']
DOI: https://doi.org/10.1038/s41699-021-00257-6